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<DIV id="content" onclick="hideTocList()"><PRE>
POSTSYN: Post Synthesis Process Radiant Software (64-bit) 2022.1.0.52.3
Command Line: postsyn -a iCE40UP -p iCE40UP5K -t SG48 -sp High-Performance_1.2V -oc Industrial -top -w -o awg_fpga_impl_1_syn.udb -ldc C:/Users/zyx/my_designs/awg_fpga/impl_1/awg_fpga_impl_1.ldc -gui -msgset C:/Users/zyx/my_designs/awg_fpga/promote.xml awg_fpga_impl_1.vm 
   Architecture:     iCE40UP
   Device:           iCE40UP5K
   Package:          SG48
   Performance:      High-Performance_1.2V
Reading input file 'awg_fpga_impl_1.vm' ...
Reading constraint file 'C:/Users/zyx/my_designs/awg_fpga/impl_1/awg_fpga_impl_1.ldc' ...
Removing unused logic ...
Starting design annotation....
 
Constraint Summary:
   Total number of constraints: 0
   Total number of constraints dropped: 0
 
Writing output file 'awg_fpga_impl_1_syn.udb'.
POSTSYN finished successfully.
Total CPU Time: 0 secs 
Total REAL Time: 0 secs 
Peak Memory Usage: 37 MB


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